1. Field of the Invention
The present invention relates to a random access memory (RAM) and, more particularly, to a high storage capacity RAM in which a memory cell array consists of a plurality of blocks arranged in the direction of digit lines, each of these blocks being equipped with a row decoder, a column decoder and a sense amplifier.
2. Description of the Prior Art
A high storage capacity RAM as an integrated circuit device includes in general a plurality of blocks arranged in the digit line direction in order to facilitate a pattern layout and to alleviate restrictions on the functions of the digit system circuit such as a column decoder and a sense amplifier. For example, the memory cell array of a 1 megawords.times.4 bits/word RAM (1M.times.4 bit RAM) consists of four blocks each having a matrix construction of 256 words.times.4,096 bits/word. Each of these blocks has a row decoder, a column decoder and a sense amplifier arrayed in the direction of word lines.
Further, the RAM has a block decoder operating in response only to a row selection signal RAS. The output of the block decoder is supplied to the row decoders and the column decoders to designate one block to be accessed. In a block thus designated, access to the memory cells is accomplished by selecting one of 256 word lines under control of the row decoder and further selecting four lines of 4,096 digit lines under control of the column decoder. On the completion of the access, the potentials of the selected word line and the selected digit lines go back to the nonselective levels.
The RAM is frequently subjected to an access mode in which one address is accessed continuously. Such an access mode is called "page mode" or "static column mode" (represented collectively by "page mode" hereinafter). The continuous address in this case is generally designated by consecutive column addresses for the same row address. Accordingly, redriving of the word lines is not needed so long as the access address remains at an address on the same word line, and in that case it has only to be done to sequentially read data from the memory cell onto the digit lines or to introduce write data to the digit lines from the outside to write the same to the memory cells.
Furthermore, a certain address range is often accessed repeatedly in response to repetition in execution of a subroutine program. In this case, depending upon the scale of the address range, the system recurs to the address on the word line that was accessed last.
However, in the above-mentioned conventional RAM, the potentials of the digit lines return to the values prior to the access every time the access is completed. For this reason, when the read operation is to be carried out by recurring to the address on the word line accessed last, it is necessary to start allover again from the driving of the word lines. As a result, the memory access time as well as the memory access cycle time are prolonged accordingly.
Moreover, since address information for selecting one digit line within one block is supplied to a column decoder, the memory access operation in the page mode for an address range that extends over a plurality of blocks is impossible.